The invention relates to a semiconductor device formed by integrating MOS (Metal-Oxide-Semiconductor) devices, and in particular to a semiconductor device having gate dielectrics for a plurality of different types of MOS devices, as well as a method for fabrication thereof.
In semiconductor devices comprising MOS devices such as MOS transistors as basic constituent elements, those utilizing MOS devices of different required performances such as memory cells and peripheral circuits, digital circuits and analog circuits, and devices requiring high speed operation and devices requiring low power consumption are present together are used more often. To satisfy respective performance requirements for different MOS devices, it is effective to form multiple MOS devices having gate dielectrics different from each other. The technique for attaining the same includes, for example, a multi-level gate dielectric technique. Semiconductor devices having multiple MOS devices formed by disposing silicon dioxides of multi-level thickness together have been generally mass produced.
In United States Patent Application Publication No. US2005/0029600A1, Tsujikawa et al. disclose a method for forming a semiconductor device of 3-thickness level comprising a gate dielectric formed of oxygen-containing silicon nitride, a gate dielectric formed of silicon dioxide not substantially containing nitrogen, and a gate dielectric formed of nitrogen-containing silicon dioxide. However, in the above method, a gate dielectric in a first domain is covered by a sequentially formed CVD silicon dioxide layer. Since the gate dielectric also comprises silicon dioxide, such that the gate dielectric may be over-etched and reined in a sequential DHF solution for removing the portion of the CVD silicon dioxide layer covering thereof or the CVD silicon dioxide layer covering the gate dielectric in the first domain may be insufficiently removed. Functionality of a semiconductor device of such 3-thickness level is thus degraded.